The present invention relates generally to an integrated circuit (IC) and the fabrication of an integrated circuit. More particularly, the present invention relates to an integrated circuit with transistors having multiple threshold voltage values.
Ultra-large-scale integrated (ULSI) circuits generally include a multitude of transistors, such as, more than one million transistors and even several million or more transistors, that cooperate to perform various functions for an electronic component. Some transistors on the integrated circuit (IC) or chip are part of circuits which perform different operations than other circuits.
Some transistors perform functions for circuits in the critical signal path of the IC, where speed is crucial to the proper operation of the IC. In contrast, other transistors perform functions for circuits in the noncritical signal path of the IC, where speed is not as important. Transistors in the non-critical signal path are preferably designed to consume less power than transistors in the critical signal path. Still other transistors may perform functions for a signal path having a criticality somewhere between the critical signal path and the non-critical signal path and, accordingly, have different speed and power consumption requirements.
Generally, transistors which have higher threshold voltages (Vth) consume less power than transistors which have low threshold voltages due to smaller off-state current leakage. Threshold voltage refers to the minimum gate voltage necessary for the onset of current flow between the source and the drain of a transistor. Transistors which have lower threshold voltages are faster (e.g., have quicker switching speeds) than transistors which have higher threshold voltages.
Currently, deep-submicron CMOS is the primary technology for ULSI devices. Over the last two decades, reduction in the size of CMOS transistors has been a principal focus of the microelectronics industry. However, as the sizes of the various components of the transistor are reduced, operational parameters and performance characteristics can change. Appropriate transistor performance must be maintained as transistor size is decreased.
One of the major roadblocks to transistor miniaturization is. related to subthreshold voltage characteristics. The subthreshold voltage characteristic refers to the relationship between voltage and current at gate voltages below the threshold voltage of the transistor (e.g., below turn-on voltages of the transistor). Generally, the threshold voltage characteristic of a transistor does not necessarily scale or change proportionally with the size of the transistor. The slope of the subthreshold voltage characteristic is related to (In 10)(kT/q) where k is the Boltzman constant, T is absolute temperature, and q is the charge of electrons. As demonstrated by the above equation, a portion of the subthreshold voltage characteristic is independent of oxide thickness, channel length, and supply voltage. Thus, transistor performance at subthreshold voltage levels does not scale with respect to transistor structures and characteristics, such as, oxide thickness, channel length, and supply voltage.
Generally, the current at subthreshold voltage levels (e.g., the leakage current) in a transistor, such as, a MOSFET, increases exponentially as the threshold voltage decreases. Therefore, to maintain off-state current within standard specifications, the threshold voltage cannot be reduced appreciably in conventional ICs or chips. The current associated with subthreshold voltages is present whether or not the transistor is in operation and can cause the integrated circuit to have a high passive power output, which is particularly troublesome for low-power or portable systems.
Transistors, such as, metal oxide semiconductor field effect transistors (MOSFETs), are generally either bulk semiconductor-type devices or silicon-on-insulator (SOI)-type devices. Most integrated circuits are fabricated in a CMOS process on a bulk semiconductor substrate.
In bulk semiconductor-type devices, transistors, such as, MOSFETs, are built on the top surface of a bulk substrate. The substrate is doped to form source and drain regions, and a conductive layer is provided between the source and drain regions. The conductive layer operates as a gate for the transistor; the gate controls current in a channel between the source and the drain regions. As transistors become smaller, the body thickness of the transistor (or thickness of depletion layer below the inversion channel) must be scaled down to achieve superior short-channel performance.
Conventional SOI-type devices include an insulative substrate attached to a thin-film semiconductor substrate that contains transistors similar to the MOSFETs described with respect to bulk semiconductor-type devices. The insulative substrate includes a buried insulative layer separating an upper semiconductor layer from the lower semiconductor base layer. The transistors on the insulative substrate have superior performance characteristics due to the thin-film nature of the semiconductor substrate and the insulative properties of the insulative substrate.
In a fully depleted (FD) MOSFET, the body thickness is so small that the depletion region has a limited vertical extension, thereby eliminating link effect and lowering hot carrier degradation. For example, a thin film FD SOI MOSFET can eliminate the need for an ultra-shallow junction which is a major challenge for proper transistor scaling. The superior performance of SOI devices is manifested in superior short-channel performance (i.e., resistance to process variation in small size transistor), near-ideal subthreshold voltage swing (i.e., steep subthreshold slope, good for low off-state current leakage), high saturation current, reduced junction capacitance, reduced junction leakage current, enhanced drive current, etc.
In ULSI circuits, transistors, such as, MOSFETs, with low threshold voltages can be used in logic paths which have high speed requirements. In contrast, transistors, such as, MOSFETs, with higher threshold voltages can be used in the non-critical signal path (e.g. storage devices), thereby reducing the off-state leakage current and, hence, reducing the standby power consumption of the entire IC.
ULSI circuits are generally manufactured in accordance with complementary metal oxide semiconductor (CMOS) technology and design criteria which utilize N-channel MOSFETs and P-channel MOSFETs. The N-channel and P-channel MOSFETs generally include a polysilicon gate structure disposed between a drain and a source. The polysilicon gate structure controls charge carriers in a channel region to turn the transistor on and off.
According to conventional bulk designs, multiple threshold voltages for transistors on a single IC are obtained by selectively providing channel implants for the transistors. Additional channel implants (e.g., doping the channel region to change the work function difference between the gate and the channel) are used for those transistors with higher threshold voltage requirements (e.g., Vth greater than 0.3V). The transistors which have lower voltage threshold requirements (e.g., Vthxe2x89xa60.2V-0.3V) do not receive the additional channel implants.
Utilizing channel implants to adjust the threshold voltages of transistors can be problematic because transistor short-channel performance is very susceptible to process variations. In particular, short-channel performance is extremely sensitive to channel implants or additional doping steps. Accordingly, the modification of the channel with implants can result in significantly different short-channel performance between transistors, which adversely affects the predictability of the design and operability of the IC. This characteristic is particularly problematic as transistors become smaller and packing densities increase. Additionally, providing channel implants adds additional steps to the fabrication process and makes the IC more difficult to manufacture.
Multiple threshold voltage devices can be particularly advantageous if a semiconductor-on-insulator or silicon-on-insulator (SOI) substrate is used. As stated above, junction capacitance is significantly reduced in SOI devices, especially in FD MOSFETs. Junction capacitance adversely affects the operational characteristics of the device. FD SOI MOSFETs also have a significantly lower subthreshold voltage slope. Therefore, the current at subthreshold voltage levels is lower when compared with conventional MOSFET at the same threshold voltage.
Certain FD SOI MOSFETs have differed from traditional MOSFETs in which the channel or body is adoped to adjust the threshold voltage. These MOSFETs have utilized a non-doped channel or body. The non-doped channel is generally preferred for thin-film FD SOI MOSFETs because it reduces random dopant fluctuation effects which adversely affect device electrical performance. However, adjustments to threshold voltages for these MOSFETs cannot be achieved through channel doping because the channel is undoped.
Thus, there is a need for an integrated circuit or electronic device that includes transistors having different threshold voltage levels which can be manufactured according to a simpler process. Further still, there is a need for an ULSI circuit that does not utilize channel implants to adjust threshold voltages among transistors. Even further still, there is a need for a process for fabricating transistors having multiple threshold voltages that is higher in density and can be more efficiently manufactured. Yet further still, there is a need for a FD SOI integrated circuit with multiple threshold voltages. Even further, there is a need for a transistor design in which the threshold voltage is locally adjustable or tunable.
An exemplary embodiment relates to an integrated circuit. The integrated circuit includes a number of gate structures. The gate structures are each disposed between a source region and a drain region. A first gate structure of the gate structures includes a first ultra-thin metal layer, and a second gate structure of the gate structures does not include the first ultra-thin metal layer. The first ultra-thin metal layer affects a work function associated with the first gate structure.
Another exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes a number of transistors. The transistors include a first transistor having a first threshold voltage and a second transistor having a second threshold voltage. The first threshold voltage is different than the second threshold voltage. The method includes providing a mask above a first gate area for the first transistor and exclusive of a second gate area for the second transistor, providing a first metal layer above the mask and above the second gate area, and removing the mask and the first metal layer above the mask. The method further includes providing a gate material above the first gate area and above the metal layer above the second gate area.
Still another exemplary embodiment relates to a method of manufacturing an integrated circuit on a semiconductor-on-insulator substrate. The method includes providing a dielectric layer over the semiconductor-on-insulator substrate, providing a first metal layer over the gate dielectric layer, providing a mask over a first area of the first metal layer, providing a second metal layer over the mask and over a portion of the first metal layer, and forming a first gate structure. The first gate structure includes the first metal and does not include the second metal layer. The method further includes forming a second gate structure. The second gate structure includes the first metal layer and the second metal layer.